1. Technical Field
The present invention relates to a method for manufacturing a semiconductor substrate, a method for manufacturing a semiconductor device, and the semiconductor device. In particular, the invention relates to a technology to form a silicon-on-insulator (SOI) structure on a semiconductor substrate.
2. Related Art
Field effect transistors formed on an SOI structure have a huge benefit in which semiconductor devices having them can achieve low power consumption and high-speed operation. This is because the field effect transistors on the SOI structure have smaller junction capacitance, which is capacitance between a source-drain region and a substrate, compared with those formed on a bulk silicon wafer.
Accordingly, a semiconductor device that can include both a transistor on a bulk silicon wafer, which is capable of operating a load requiring large power consumption, and a transistor formed on an SOI structure has been known.
Further, as a method to isolate elements, a local oxidation of silicon (LOCOS) film is used.
In a common method thereof, an SOI substrate having an SOI structure formed on the entire surface of a bulk silicon wafer is prepared first, and then transistors are sequentially formed on the SOI structure. The SOI structure formed in an unwanted area is removed thereafter.
Further, a separation by bonding Si islands method capable of manufacturing an SOI transistor economically by partially forming an SOI structure on a bulk silicon wafer is disclosed.
In the method to partially form an SOI structure on a bulk silicon wafer, an insulating film such as a silicon oxide film is formed to cover the SOI structure to isolate the SOI structure from other portions. Then, the insulating film is planarized by chemical mechanical polishing (CMP). (e.g. T, Sakai et al., Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)).
When a surface of a silicon layer is exposed by planarization using CMP, the surface of the silicon layer may be scratched due to variation in polished amounts.
Therefore, CMP is performed to leave a sufficient thickness of the insulating film to avoid scratching the silicon layer, then, wet etching needs to be performed. That is, the thick insulating film needs to be etched by wet etching after CMP.
When the thick insulating film is etched by wet etching, variation in wet etching amounts becomes large in proportion to an amount and time of wet etching, making the surface to be exposed uneven. Consequently, when the surface of the silicon layer is fully exposed by wet etching, corners of the silicon layer are widely exposed, causing occurrence of a parasitic MOS and deterioration of the reliability of the insulating film.